• Device and circuit level optimization of digital building blocks. Circuit design styles for logic, arithmetic, and sequential blocks. Estimation and minimization of energy consumption. Interconnect models and parasitics, device sizing and logical effort, timing issues (clock skew and jitter), and active clock distribution techniques. Memory architectures, circuits (sense amplifiers), and devices. Evaluation of how design choices affect tradeoffs across key metrics including energy consumption, speed, robustness, and cost. Extensive use of modern design flow and EDA/CAD tools for the analysis and design of digital building blocks and digital VLSI design for labs and design projects

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